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Complex-Block Characterization
includes
computationally intensive verification tasks from pre- and post-layout
simulation to variation, noise, and RF analysis on circuits such as
PLLs, DLLs, ADCs, SerDes, Tx chains, Rx chains, and memory interfaces.
Nanometer-scale analog/RF circuits are very susceptible to variations
in process, voltages, and temperatures, especially when implemented in
CMOS. Given the level of integration and associated mask set and
silicon costs, ensuring yield prior to tapeout is increasingly
important. Doing so requires running across an increasing number of
corners or moving to Monte Carlo. Generally this means running 10, 100,
or more full accuracy transient simulations – potentially
including
parasitics. These simulations absolutely require nanometer SPICE accuracy to
trust the quantitative results, let alone discern the sometimes subtle
variances between iterations. This massive task occurs at the end of
the design cycle where schedule pressures are highest and compute
resources are often at a premium.
Complex-Block
Variation Analysis Examples
The first example in the table above is a 65nm PLL for a high-volume,
high-end SoC. The design team used extensive corner analysis to ensure
the circuit was going to have sufficiently high yield. Their
traditional SPICE simulator took 7-10 days to run each corner. In order
to get this done as quickly as possible, they set up a dedicated
30-server farm running traditional SPICE. Even so, it took >2
weeks
to complete. Just as importantly, since each run took at least a week
they could not get their first results back until that long.
One Analog
FastSPICE (AFS) license running on a single-CPU finished a
corner in 20
hours – 9x faster with identical results for every node. With
only 5
AFS licenses, the design team could finish the analysis in about half
the time as their 30-SPICE simulator farm – and they would
get results
from the first 5 corners in less than 1 day, the next 5 in less than 2
days, etc. So, they could catch any early problems up to 6 days sooner.
When the design team subsequently ran a new 55nm PLL, traditional SPICE
took 3-4 weeks to complete a corner. AFS completes a corner in 3-4 days.
The second PLL in the table was also targeted for a high-volume SoC.
Although the designers wanted to run Monte Carlo with at least 50
iterations, they deemed doing so as infeasible because each iteration
required 2.3 days with their traditional SPICE simulator. AFS delivered
the identical results in only 2.6 hours – 20x faster
– making Monte
Carlo practical.
The Burst Read Path example is one of many tests for a leading-edge
flash memory circuit. Traditional SPICE could not converge on the
circuit, which had nearly 100K total elements and over 45K transistors.
To get around this problem, the designer ran a digital fastSPICE
simulator to generate initial conditions to feed into their traditional
SPICE simulator. The same setup worked for 4 corners at most, so the
designer needed to change the setup several times to complete all 9
corners. The total runtime was 2.5 days per corner. AFS converged and
ran every corner with no need for fastSPICE-generated initial
conditions and each corner required only 2 hours – 30x faster.
The final example in the table illustrates the value of AFS for
modest-sized circuits that require extensive Monte Carlo analysis. The
designer was running a 500-iteration Monte Carlo analysis on an
amplifier that had only 1.1K total elements. The total runtime was 4.6
hours, which is ~33 seconds per iteration. Although Berkeley Design
Automation targets much larger simulations with AFS, in this case the
tool delivered identical results 8.5x faster, cutting each iteration to
less than 4 seconds.
Click here to continue to Complex Block: Device Noise
Analysis.
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