High-Speed I/O Verification

Inter-chip communication over high-speed serial I/O (HSIO) channels is now the norm, with numerous standardized protocols, such as PCI Express, HyperTransport, DDR3, XDR, GigaBit Ethernet, etc. With multiple Gbps signal rates (e.g., 8 Gbps PCI Express v3.0 data rate per lane), recovered clock jitter limits overall system performance. At these rates, accurately verifying total jitter with all contributing physical effects and under all expected conditions is critical. This must include device noise, which is a major contributor to jitter in nanometer process nodes, and parasitics, which contribute to frequency-dependent channel attenuation.

A typical HSIO architecture is shown in the diagram above. In many such circuits the serializer contains a retimer, ensuring that output data is multiplexed correctly to the output serial stream. Phase mismatch between these data (here determined by clk0 and clk180) results in deterministic jitter applied to the serial data stream. Total system jitter is the sum of this deterministic jitter and the random jitter associated with device and system noise. The key circuits that impact output jitter include PLL, CDR, Equalizer, and any other custom block in the signal path. The table below shows specifications for a typical nanometer-scale HSIO transceiver—in this case PCI Express v3.0.

Eye diagrams capture HSIO signal quality over many bit transitions, including the inter-symbol interference from any modeled non-idealities such as reflections, loss, jitter and noise. The example below shows both transmit and receive eyes, with random and deterministic jitter superimposed on the receive eye. This diagram also shows the Bit Error Rate (BER) Compliance Zone. A target BER of 10-12 means that out of 1012 received bits, one may be in error. Since simulating 1012 bits is not feasible, designers must extensively verify HSIO blocks, and then analyze the full-circuit as thoroughly as practical – again with critical physical effects. Hence, simulation accuracy, performance, capacity, and device noise analyses are all critical.

Meeting HSIO Verification Challenges

Verifying high-speed I/O circuits raises a number of difficult verification challenges at the block, complex-block (e.g., PLL, Tx, Rx), and full-circuit levels. Transient simulations must provide typically 80 dB to 120 dB of dynamic range to ensure measurements to the specification’s resolution. This translates to SPICE tolerances that are one to several orders of magnitude tighter than default SPICE (e.g., reltol = 1E-4 to 1E-6). Verifying the jitter specifications requires including device noise to the same degree of accuracy with a device noise bandwidth that is 50x the clock frequency. Block-level simulations require 100s or 1000s of iterations to ensure every block meets specifications at all VT corners with global process variation, device mismatch, device noise, and detailed parasitics.

The Analog FastSPICE Platform (AFS) provides the world’s fastest nm circuit verification and is ideally suited for verifying high-speed I/O. With a proven >120 dB dynamic range, it is 5x-10x faster than any other SPICE accurate simulator on a single core. For long runs, it employs multithreading for the ultimate sequential run performance. Importantly, its >10M element capacity enables verification of full circuits with detailed parasitics.

To accurately measure jitter, the AFS Platform provides the world’s only full-spectrum device noise analyses for every type of circuit. For non-periodic circuits such as PLLs, Tx, and Rx path, it employs parallel transient noise analysis that is 5x-10x faster than any other simulator. It’s the only tool proven to consistently deliver measurements within 1 dB to 2 dB of silicon.

To meet HSIO intensive block-level characterization requirements, AFS assigns corner, sweep, and Monte Carlo iterations to independent cores, each of which uniquely provides nanometer SPICE accuracy 5x-10x faster than traditional SPICE. Hence it is able to deliver nearly linear speedup with the number of cores. AFS effectively turns a multicore computer into the equivalent of a full simulation farm.

For challenging high-speed I/O applications, Analog FastSPICE delivers the most accurate, most comprehensive, and highest-performance verification capabilities available in a single-executable platform.

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