2011 Nanometer Circuit Verification Forum

On Sept. 22, Berkeley Design Automation hosted the 2011 Nanometer Circuit Verification Forum, at the TechMart in Santa Clara, CA. The event had over 100 attendees, who saw 15 user presentations, drawn from active customers, university researchers, and EDA partners. The presenters related their experiences of how the Analog FastSPICE (AFS) Platform delivers vastly superior performance and more accurate device noise analysis than other “golden” circuit simulators. These users described how in many cases AFS saves weeks or even months of simulation time or enables efficient circuit verification that has never been possible - or even attempted - before.  

The day started out with the keynote address from industry luminary Jim Hogan, covering highlights from his extensive career in semiconductors and EDA, and looking forward to key future challenges in nanometer circuit verification. Jim made the case that the changing scale of physics requires much higher performance transistor-level simulation while not sacrificing traditional SPICE accuracy. He also sees continued opportunities for innovative algorithmic and numerical techniques to address ever deeper process and complexity issues.  

For the rest of the day, presenters from industry and universities described how AFS is used to verify data converters (DACs and both over-sampled and Nyquist ADCs) and closed-loop PLLs, including the impact of device noise, to within 1 or 2dB of silicon characterization. For the majority of circuits AFS was consistently 5X to 30X faster than other simulators, with superior silicon correlation. In many cases, AFS was the only simulator that could converge, deliver accurate results, or run in a time frame of relevance. A presentation from Silicon Creations, highlighted in the figure below, reported that AFS results for the locking of a Frac-N PLL match silicon measurement and is 18x faster than traditional SPICE. [1]

A broad range of additional circuits was also presented, from VCOs to entire top-level SerDes circuits (including two PLLs, one for clock and data recovery and one for transmit clock generation). The presentations also included new verification methodologies, for example, the use of variable domain translators to perform linear AC analysis in non-voltage domains, allowing DLL/PLL delay and phase transfer function to be easily computed, as well as supply noise impact on delay and phase, and DLL/PLL bandwidth.  

Several Berkeley Design Automation EDA partners presented their own unique nanometer-focused solutions, each leveraging the AFS Platform for circuit simulation. The companies included Accelicon, Ciranova, Invarian, MunEDA, and Solido. The day ended with a demonstration session and reception.

 [1] A. Cole et al, “AFS used in PLLs, ADCs & SerDes; Real-world Performance”,
      Silicon Creations

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