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The following are
additional features of the AFS
Circuit Simulator.
AFS Co-Simulation
AFS
Co-Simulation
supports HDL co-simulation with leading Verilog
simulators and gives design teams the fastest
full-circuit & post-layout transistor-level
verification. AFS Co-Simulation supports the
standard SPICE-Verilog use
model, includes mixed-analog and digital debugging, and integrates with
industry-leading PLI 2.0 compliant Verilog simulators.
AFS
Mega-Solvers
AFS Mega-Solvers are
high-capacity high-performance matrix solvers
that are optimized for massive circuits, including circuits with high
parasitic
ratios. AFS
Mega-Solvers include:
- Proven
>10M-element capacity for full-circuit simulation
- Auto-selected to maximize performance
- Multi-core
support and parasitic acceleration
- No
block-level tuning
- Automatic
performance estimation
- Automatic
simulator and analysis option recommendations
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